The present invention relates to integrated circuits for data communication systems such as network devices and telecommunications circuits. More particularly, the present invention relates to a multiple channel data buffer for use in an integrated circuit having multiple I/O ports.
Network devices and telecommunication circuits typically have several communication channels for connecting to multiple devices such as computer work stations, telephone and television systems, video teleconferencing systems and other facilities over common data link support carriers.
Personal computers and computer work stations are typically interconnected by local area networks (LANs) such as Ethernet, Token Ring, DECNet and RS-232, whereas remote systems are interconnected by wide area networks (WANs) such as V.34, ISDN Basic Rate Interface (BRI), Frame Relay (T1/E1 or fractional T1/E1), Asynchronous Transfer Mode (ATM) links, ADSL and High Level Data Link Control (HDLC) networks.
In these applications, it is common to use a first-in-first-out (FIFO) buffer for buffering transmit and receive data through each channel. Typically, each communication channel has its own transmit FIFO and receive FIFO. Each FIFO uses a dual port random access memory (RAM) for storing the data. One port is used by the I/O port of the communication channel and the other port is used by a data routing circuit which routes the data between the FIFO and a memory or other device. This structure is not very scalable on an integrated circuit since RAMs have specific layout restrictions on the integrated circuit. For example, RAMs are often required to be placed on an edge of the integrated circuit die. This makes it difficult to place a large number of RAMs on a single integrated circuit and thus limits the number of communication channels that can be supported on the integrated circuit. Improved data communication buffer circuits are desired.